Deep pipelined devices such as but not limited to on-chip interconnects, can interface with many components. Requests to receive a service or gain access to a certain bus are usually sent to an arbitrator that can apply various arbitration schemes in order to determine which service shall be granted or which component can gain access to a shared medium such as a shared bus.
The arbitration schemes can be responsive to the priority of the requesting component. Accordingly, more important components such as processors, digital signals processor and the like are associated with higher request priority. In deep pipelines devices' requests to receive a service can propagate through many pipeline stages before getting to the arbiter. These pipelines stages actually form a request queue in which lower priority request can be located before high priority requests.
There is a need to provide an efficient device having priority upgrade capabilities and methods for upgrading capabilities